Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
Xilinx 100Gb/s AES-GCM Crypto IP for MACsec
Description
The 100G AES-GCM Crypto IP is a full-featured implementation of the AES-GCM algorithms for IEEE 802.1AE Media Access Control Security (MACsec) specification, targeted for the Xilinx UltraScale and UltraScale+ FPGAs.
Version
100Gb/s AES-GCM (MACsec) v1.0 (Firmware)
Type
FIRMWARE
Vendor
Advanced Micro Devices (AMD)
2485 Augustine Drive
Santa Clara, CA 95054
USA
Contacts
FIPS Contact
FIPS@amd.com
+1 408-749-4000

AES 3953

   First Validated: 4/29/2016
Operating Environment Algorithm Capabilities
Cadence IUS 14.10.018 Verilog Simulator AES-ECB Expand
Cadence IUS 14.10.018 Verilog Simulator AES-GCM Expand
Cadence IUS 14.10.018 Verilog Simulator AES-GMAC Expand

Created October 05, 2016, Updated February 20, 2025