Projects
Cryptographic Algorithm Validation Program
Cryptographic Algorithm Validation Program CAVP
Description
The 100G AES-GCM Crypto IP is a full-featured implementation of the AES-GCM algorithms for IEEE 802.1AE Media Access Control Security (MACsec) specification, targeted for the Xilinx UltraScale and UltraScale+ FPGAs.
Version
100Gb/s AES-GCM (MACsec) v1.0 (Firmware)
Vendor
Contacts
Ravi Sunkavalli
rsunkav@xilinx.com
(408) 879-3557
Operating Environment |
Algorithm Capabilities |
Cadence IUS 14.10.018 Verilog Simulator
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AES-ECB
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Cadence IUS 14.10.018 Verilog Simulator
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AES-GCM
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Cadence IUS 14.10.018 Verilog Simulator
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AES-GMAC
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Created October 05, 2016, Updated January 22, 2021