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Combinatorial Methods for Trust and Assurance

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ACTS Library

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Quick start Downloadable Tools Fundamental background papers Tutorials and Documentation Combinatorial Methods in Testing Why do Combinatorial Testing? Event Sequence Testing Case Studies Assured autonomy - AI Safety and Security AI-Enabled Systems Explainable AI, Verification, and Validation Rule-based Expert Systems and Formal Methods AI and Assured Autonomy Papers Assured Autonomy - briefings and videos Case studies Hardware and Embedded Systems Semiconductor Functional Verification Technical Plan Benefits Physical Unclonable Function (PUF) Vulnerabilities Embedded System Faults and Vulnerabilities Automated Testing Automated Test Generation Oracle-free Testing Property based Testing Input space measurement for autonomy and testing Input Space Coverage Measurement Coverage examples Case studies Cybersecurity Testing Combinatorial approach MagicMirror smart contract testing Case studies Software Testing Methodology NIST Testing Process DOs and DON'Ts of testing ACTS Library Papers on combinatorial test methods Covering Array Library Seminars & Talks & Tutorial Combinatorial Methods For Modeling & Simulation Workshop Papers Our Research Program

Contacts

Rick Kuhn, NIST
Address: https://www.nist.gov/people/d-richard-kuhn

Raghu Kacker, NIST
301-975-2109
Address: http://math.nist.gov/~RKacker/

M S Raunak, NIST

Group

Security Components and Mechanisms

Topics

Security and Privacy: assurance, modeling, testing & validation

Technologies: semiconductors, software & firmware

Related Projects

Access Control Policy Testing

Additional Pages

Quick start Downloadable Tools Fundamental background papers Tutorials and Documentation Combinatorial Methods in Testing Why do Combinatorial Testing? Event Sequence Testing Case Studies Assured autonomy - AI Safety and Security AI-Enabled Systems Explainable AI, Verification, and Validation Rule-based Expert Systems and Formal Methods AI and Assured Autonomy Papers Assured Autonomy - briefings and videos Case studies Hardware and Embedded Systems Semiconductor Functional Verification Technical Plan Benefits Physical Unclonable Function (PUF) Vulnerabilities Embedded System Faults and Vulnerabilities Automated Testing Automated Test Generation Oracle-free Testing Property based Testing Input space measurement for autonomy and testing Input Space Coverage Measurement Coverage examples Case studies Cybersecurity Testing Combinatorial approach MagicMirror smart contract testing Case studies Software Testing Methodology NIST Testing Process DOs and DON'Ts of testing ACTS Library Papers on combinatorial test methods Covering Array Library Seminars & Talks & Tutorial Combinatorial Methods For Modeling & Simulation Workshop Papers Our Research Program

Contacts

Rick Kuhn, NIST
Address: https://www.nist.gov/people/d-richard-kuhn

Raghu Kacker, NIST
301-975-2109
Address: http://math.nist.gov/~RKacker/

M S Raunak, NIST

Group

Security Components and Mechanisms

Topics

Security and Privacy: assurance, modeling, testing & validation

Technologies: semiconductors, software & firmware

Related Projects

Access Control Policy Testing

Created May 24, 2016, Updated September 12, 2024